Integrated input modeling and memory management for image processing applications

Image processing applications often demand powerful calculations and real-time performance with low power and energy consumption. Programmable hardware provides inherent parallelism and flexibility making it a good implementation choice for this application domain. In this work we introduce a new modeling technique combining Cyclo-Static Dataflow (CSDF) base model semantics and Homogeneous Parameterized Dataflow (HPDF) meta-modeling framework, which exposes more levels of parallelism than previous models and can be used to reduce buffer sizes. We model two different applications and show how we can achieve efficient scheduling and memory organization, which is crucial for this application domain, since large amounts of data are processed, and storing intermediate results usually requires the use of off-chip resources, causing slower data access and higher power consumption. We also designed a reusable wishbone compliant memory controller module that can be used to access the Xilinx Multimedia Board’s memory chips using single accesses or burst mode

INTEGRATED INPUT MODELING AND MEMORY MANAGEMENT FOR IMAGE PROCESSING APPLICATIONS

Image processing applications often demand powerful calculations and real-time performance with low power and energy consumption. Programmable hardware provides inherent parallelism and flexibility making it a good implementation choice for this application domain. In this work we introduce a new modeling technique combining Cyclo-Static Dataflow (CSDF) base model semantics and Homogeneous Parameterized Dataflow (HPDF) meta-modeling framework, which exposes more levels of parallelism than previous models and can be used to reduce buffer sizes. We model two different applications and show how we can achieve efficient scheduling and memory organization, which is crucial for this application domain, since large amounts of data are processed, and storing intermediate results usually requires the use of off-chip resources, causing slower data access and higher power consumption. We also designed a reusable wishbone compliant memory controller module that can be used to access the Xilinx Multimedia Board's memory chips using single accesses or burst mode

Biomedical prototype development in Uruguay: 15 years and lessons learned

NIB develops a medical device if i) a clinical team is willing to use it and share specification, ii) it contains some originality, iii) financial resources and students are available. A 32 personyear effort is analyzed from perpectives of cost, technological availability for industry, teaching and clinical utility

INTEGRATED INPUT MODELING AND MEMORY MANAGEMENT FOR IMAGE PROCESSING APPLICATIONS By

Computer Studies Image processing applications often demand powerful calculations and real-time performance with low power and energy consumption. Programmable hardware provides inherent parallelism and flexibility making it a good implementation choice for this application domain. In this work we introduce a new modeling technique combining Cyclo-Static Dataflow (CSDF) base model semantics and Homogeneous Parameterized Dataflow (HPDF) meta-modeling framework, which exposes more levels of parallelism than previous models and can be used to reduce buffer sizes. We model two different applications and show how we can achieve efficient scheduling and memory organization, which is crucial for this application domain, since large amounts of data are processed, and storing intermediate results usually requires the use of off-chip resources, causing slower data access and higher power consumption. We also designed a reusable wishbone compliant memory controller module that can be used to access the Xilinx Multimedia Board’s memory chips using single accesses or burst mode

Mapping multimedia applications onto configurable hardware with parameterized cyclo-static dataflow graphs

This paper develops methods for model-based design and implementation of image processing applications. We apply our previously developed meta-modeling technique of homogeneous parameterized dataflow (HPDF) [9] to the framework of cyclostatic dataflow (CSDF) [1], and demonstrate this integrated modeling methodology through hardware mapping of a gesture recognition application. We also provide a comparative study between HPDF/CSDF-based representation of the gesture recognition application, and a previously developed version based on applying HPDF in conjunction with conventional synchronous dataflow (SDF) semantics [9]. 1

Session R1D Laboratory at Home: Actual Circuit Design and Testing Experiences in Massive Digital Design Courses

Abstract- An innovative laboratory methodology for the digital design introductory course is presented. We replace the traditional lab experiences, where students have to come to school classrooms, with a “lab at home ” concept. More than 65 kits with a programmable logic board are given to groups of students for the whole semester. Thus, students perform all the lab stages, including analyzing the problems, designing a solution and testing the actual circuit, at their homes. Then, they come to school to show their circuits to the professors. These evaluation instances, together with a final exam, are enough to adequately evaluate the students ’ work, eliminating the need of a midterm exam. This is the third edition of the course with this methodology. A survey of opinion showed that the experience was very successful among students. Moreover, it is very suitable for massive courses and easily scalable, providing actual hardware platforms for students at an affordable cost for the institution. Index Terms – Laboratory, digital design, electronics